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Multi-channel length is a technique for reducing power leakage in both active and idle modes on CMOS technology. Other techniques to reduce leakage, like power gating and SRAM retention, are targeted at reducing leakage power when the device, or portions of it, are not operating. Short channel length devices provide higher performance than longer channel length devices, but the longer channel length has significantly reduced subthreshold leakage current. In this generation of the power management tool box, two channel lengths summarized in the table below were used for the speed vs. leakage trade-off. Timing-critical paths are constructed of short channel length cells, but for non timing-critical paths, the longer channel length cells can be used to trade off speed for lower leakage. Multiple channel length synthesis achieves up to 30% leakage reduction. One additional usage of longer channel length transistors is for always-on logic and for special power management cells (isolation cells, always on buffers, etc.) where speed is not critical. ==References== () Rusu, S.; Tam, S.; Muljono, H.; Ayers, D.; Chang, J.; Cherkauer, B.; Stinson, J.; Benoit, J.; Varada, R.; Leung, J.; Limaye, R. D.; Vora, S.; "A 65-nm Dual-Core Multithreaded Xeon Processor With 16-MB L3 Cache," Solid-State Circuits, IEEE Journal of, vol.42, no.1, pp. 17– 25, Jan. 2007, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4039601&isnumber=4039574 () Gammie, G.; Wang, A.; Mair, H.; Lagerquist, R.; Minh Chau; Royannez, P.; Gururajarao, S.; Uming Ko; "SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors," Proceedings of the IEEE, vol.98, no.2, pp. 144–159, Feb. 2010 () 40-nm FPGA Power Management and Advantages. Altera Ic. December 2008, ver. 1.2. URL: http://www.altera.com/literature/wp/wp-01059-stratix-iv-40nm-power-management.pdf 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「Multi-channel length」の詳細全文を読む スポンサード リンク
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